Reversible logic synthesis algorithmbased on cooperative multi-objective differential evolution
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摘要: 可逆逻辑电路可避免因信息丢失而产生的热耗散，从而有望解决集成电路热耗问题. 将可逆逻辑电路设计问题抽象为带有强约束的多目标优化问题，提出以协同多目标差分进化算法为核心的可逆逻辑综合方法. 该方法基于种群自适应调节的差分进化算法，结合协同进化的多种群策略优化多目标，经种群选择及自适应调节策略和Paroto最优评估评价更新候选个体. 通过求解经典电路测试集，验证了所提方法的可行性及有效性. 与经典及基于启发式算法的可逆逻辑综合方法相比，该方法生成的电路性能更优.Abstract: Reversible logic circuits can avoid thermal dissipation due to information loss so that it is possible to solve the thermal dissipation problem of integrated circuits. As reversible logic circuit synthesis problem was modeled as a multi-objective optimization problem, a reversible logic synthesis method was proposed based on a cooperative multi-objective differential evolution algorithm. Differential evolution algorithm with self-adaptive population resizing mechanism (SapsDE) was adopted as the basis and combined with the co-evolution algorithm based multiple population strategy for multiple objectives. Meanwhile, the population updating scheme and the fitness evaluation strategy based on Pareto-optimal were employed to update the candidate individuals. The synthesis method tested on a suite of benchmark functions is feasible and effective. Compared with classical and heuristic synthesis methods, the circuits generated by the proposed synthesis method have better performance.
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Key words:
- reversible logic circuit /
- differential evolution (DE) /
- co-evolution /
- multi-objective
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图 2 本研究算法法实现的部分可逆逻辑电路
Figure 2. Part of reversible logic circuits implemented by proposed method
表 1 试验参数设定
Table 1. Experimental parameters
参数 设定值 ${{\rm{st}}}_{{\rm{max}}}$ 3 种群规模下界值 200 种群规模调整因子 1 表越界及停滞临界变量R 4 最大进化代数 500 初始种群规模 500 
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表 2 各算法试验结果比较
Table 2. Comparison of results by algorithms
测试电路 本研究算法 文献[9]算法 文献[10]算法 文献[11]算法 文献[12]算法 NGO NG CQC NGO NG CQC NGO NG CQC NGO NG CQC NGO NG CQC ham3 0 5 7 0 5 7 0 5 9 — 5 9 — 5 9 f1 0 4 8 — — — 0 4 16 — 4 8 — 4 16 f2 0 3 5 — — — 0 3 7 — 3 7 — 3 7 f3 0 3 7 — — — 0 3 15 — 3 7 — 3 15 3_17 0 6 12 0 6 12 0 6 14 — 6 14 — 6 14 rd32 2 4 8 — — — 2 4 8 — — — — — — Xor5 4 4 4 — — — 4 4 4 — — — — — — 4mod5 4 5 7 4 8 24 4 5 13 — 5 13 — 5 55 rd53 5 12 36 4 12 132 4 13 116 — — — — — — ham7 0 25 47 0 23 81 0 24 68 — — — — — — 注：f1、f2和f3分别为测试电路(1 0 3 2 5 7 4 6)、(7 0 1 2 3 4 5 6)、(0 1 2 3 4 6 5 7)；“—”为对应结果缺失.
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